1. Technical Field
An operational transconductance amplifier for an output buffer that improves the current sourcing and sinking drivability for an output load is disclosed.
2. Description of Related Technology
As is well known, an operational amplifier may be connected as a buffer that enables analog signals to be input to the buffer output or driven into greater loads than would otherwise be possible without the buffer.
FIG. 1 is an exemplary circuit diagram that depicts a conventional two-stage operational amplifier that may be used in an output buffer. As shown in FIG. 1, the conventional two-stage operational amplifier includes a differential amplification unit 11, a driving unit 12 and an output load 13. The differential amplification unit 11 receives a pair of differential input signals (IN+ and INxe2x88x92) and differentially amplifies the received differential input signals. The driving unit 12 drives the output load 13 connected with an output node N12 according to the output signals of the differential amplification unit 11 and a bias voltage Vbias.
The differential amplification unit 11 includes a pair of PMOS transistors MP11 and MP12 that are used to provide an active load, a pair of NMOS transistors MN11 and MN12, having respective gates to which a pair of differential input signals (IN+ and INxe2x88x92) are applied and an NMOS transistor MN13, to which uniform bias voltage Vbias is applied.
The driving unit 12 includes a PMOS transistor MP13 that functions as a current source and an NMOS transistor MN14 for current sinking. A gate terminal of the PMOS transistor MP13 is connected to an output node N11 of the differential amplification unit 11. The transistor MP13 functions to charge the output load 13 connected to the output node N12 of operational amplifier. The NMOS transistor MN14 functions to discharge the output load 13 connected to the output node N12 using the bias voltage Vbias, which is connected to a gate terminal of the transistor MN14. The output load 13 includes a capacitor CL and a resistor RL, both of which are connected to the output node N12.
In operation, the differential amplification unit 11 receives a pair of differential input signals (IN+ and INxe2x88x92) and differentially amplifies the received signals and generates output signals having a predetermined level. When the driving unit 12 sources current to the output load unit 13, the PMOS transistor MP13 is turned on in response to a signal provided by the node N11 of the differential amplification unit 11, thereby enabling the output load 13 to be charged. On the other hand, to discharge the output load 13, the PMOS transistor MP13 is turned off and the NMOS transistor MN14 is turned on by the bias voltage Vbias.
When considering the current drivability of output load in the conventional two-stage operational amplifier, a drivability of the PMOS transistor MP13 for sourcing current is typically sufficient to charge the output load 13. However, the drivability of NMOS transistor MN14 for sinking current to discharge the output load 13 is typically limited a quiescent current state. Namely, because a fixed bias voltage Vbias is applied to a gate of the NMOS transistor MN14 to supply bias current to the differential amplification unit 11, the drivability (i.e., the current drive capability) is much lower than the current source PMOS transistor MP13. Thus, to more rapidly discharge the output load unit 13, the quiescent current of the NMOS transistor MN14 must be increased. Unfortunately, increasing quiescent current in this manner increases static power consumption of the operational amplifier.
In the case of an LCD source driver for driving each display pixel, an output buffer such as that shown in FIG. 1 may be used for each pixel. However, the amplifier shown in FIG. 1 cannot be applied to the LCD source driver due to its excessive power consumption.
FIG. 2 is an exemplary circuit diagram showing a conventional one-stage operational transconductance amplifier. As shown in FIG. 2, the conventional one-stage operational transconductance amplifier includes a differential amplification unit 21, a driving unit 22 and an output load 23. The differential amplification unit 21 receives a pair of differential input signals (IN+ and INxe2x88x92) and differentially amplifies the received differential input signals (IN+ and INxe2x88x92). The driving unit 22 drives the output load 23, which is connected to an output node N23, by a first output signal and a second output signal of a first output node N21 and a second output node N22, respectively, in the differential amplification unit 21.
The configuration of the differential amplification unit 21 is generally similar to the differential amplification unit 11 shown in FIG. 1. In FIG. 1, the gates of the PMOS transistors MP11 and MP12, which are passive loads, are connected to each other and to a drain of the NMOS transistor MN11. On the other hand, in the differential amplification unit 21 shown in FIG. 2, the gates of PMOS transistors MP21 and MP22 are connected to the drains of NMOS transistors MN21 and MN22, respectively, and the drains form a first output node N21 and a second output node N22, respectively.
The driving unit 22 includes a PMOS transistor MP24 for sourcing current to charge the output load 23 in response to the second output signal of the second output node N22 in the differential amplification unit 21, a PMOS transistor MP23 and an NMOS transistor MN24 to supply bias current for current sinking in response to the first output signal of the first output node N21 in the differential amplification unit 21 and an NMOS transistor MN25, which is driven by the current supplied through the PMOS transistor MP23 and the NMOS transistor MN24, for sinking current to discharge the output load 23. The output load 23, which is identical to the output load 13 as shown in FIG. 1, includes a capacitor (CL) and resistance (RL).
In operation, the differential amplification unit 21 receives a pair of differential input signals (IN+ and INxe2x88x92) and differentially amplifies the received input signals and then the first and the second output signals are output through the first and second output nodes N21 and N22. To source current to the output load 23, the PMOS transistor MP24 is turned on in response to the second output signal outputted through the second output node N22 in the differential amplification unit 21.
To sink current from the output load 23, a current mirror is formed at the PMOS transistor MP23, having a gate to which the first output signal of the first output node N21 in the differential amplification unit 21 is applied, with the PMOS transistor MP21 in the differential amplification unit 21 and the current flows into the NMOS transistor MN25 for current sinking through the NMOS transistor MN24.
Accordingly, in the conventional one-stage operational transconductance amplifier, as the NMOS transistor MN25 for sinking current and the PMOS transistor MP24 for sourcing current are driven in response to the output signals of the first and second output nodes N21 and N22, respectively, the current I/2 flowing through the PMOS transistor MP24 increases in proportion to the size ratio of the PMOS transistors MP24 and MP22.
Generally speaking, it is advantageous that the drivability for sourcing current and the drivability for sinking current of the output load 23 in the conventional operational transconductance amplifier are identical. However, there is a problem that the maximum driving current of the PMOS transistor MP24 for sourcing current and the NMOS transistor MN25 for sinking current of output the load 23 is limited to two times the quiescent state current.
Because the uniform bias voltage Vbias is applied to the gate of the NMOS transistor MN23 in the differential amplification unit 21, current I always flows at the NMOS transistor MN23 so that a current I/2 flows through each of the NMOS transistors MN21 and MN22 in the quiescent state.
The current I/2 for each PMOS transistor MP24 and NMOS transistor MN25 increases in proportion to the size ratio of the PMOS transistors MP24 and MP22 and a size ratio of the NMOS transistors MN25 and MN24 by a current mirror. Alternatively, when current I flows through only one of the NMOS transistors MN21 or MN22, the current I of the PMOS transistor MP23 or the NMOS transistor MN25 increases in proportion to a size ratio of the PMOS transistors MP24 and MP22 and a size ratio of the NMOS transistors MN25 and MN24 so that the maximum driving current is two times the quiescent state current.
The conventional one-stage operational amplifier has a low gain characteristic due to a one-stage structure and the fact that it has identical current sinking and current sourcing drive capability. However, the maximum driving current is limited to two times the quiescent state current. Because the quiescent current must be increased to drive a large capacitive load, which undesirably increases power consumption.
FIG. 3 is an exemplary circuit diagram that depicts a conventional push-pull operational amplifier that may be used for driving a large capacitive load. As shown in FIG. 3, the conventional push-pull operational amplifier includes a differential amplification unit 31 for receiving a pair of differential input signals IN+ and INxe2x88x92 and differentially amplifies the differential input signals. The push-pull amplification unit 31 also includes a driving unit 32 for driving an output load 33, which is connected to an output node N33, in response to first and a second output signals of first and second output nodes N31 and N32.
The differential amplification unit 31 is similar to the differential amplification units 11 and 21 shown in FIGS. 1 and 2. In the conventional push-pull operational amplifier, gates of the PMOS transistors MP31 and MP32 are connected to each other and joined to a drain of the PMOS transistor MP31. Drains of the PMOS transistors MP31 and MP32 are represented as the first and second output nodes N31 and N32, respectively.
The driving unit 32 includes a PMOS transistor MP34 for current sourcing, a PMOS transistor MP33 and an NMOS transistor MN34 for supplying bias current and an NMOS transistor MN35 for current sinking. The PMOS transistor MP34 for current sourcing charges the output load 33 in response to the second output signal of the second output node N31. The PMOS transistor MP33 and the NMOS transistor MN34 supply bias current in response to the first output signal of the first output node N31 in the differential amplification unit 31 and the NMOS transistor MN35 for current sinking, which is driven by the bias current supplied through the PMOS transistor MP33 and the NMOS transistor MN34, are for discharging the output load 33. The output load 33 includes a capacitor and a resistance.
In operation, the differential amplification unit 31 receives a pair of differential input signals (IN+ and INxe2x88x92) and outputs first and second output signals through the first and second output nodes N31 and N32 after differentially amplifying the received differential input signals. To source current to the output load 33, the driving unit 32 drives the PMOS transistor MP34 using the output signal of the second output node N32 in the differential amplification unit 31.
On the other hand, for sinking current from the output load 33, a current mirror is formed at the PMOS transistor MP33, having a gate to which the output signal of the first output node N31 is applied. A bias current is supplied to the NMOS transistor MN35 for current sinking through the diode-connected NMOS transistor MN34 so that the output load 23 is discharged.
In the conventional push-pull operational amplifier, because the PMOS transistor MP34 for current sourcing is driven by the output signal of the second output node N32 in the same manner shown in FIG. 1, a sufficient drivability of the current source can be achieved.
The uniform bias voltage Vbias is not applied to the gate of the NMOS transistor MN35 for current sinking different from FIG. 1. The gate of the NMOS transistor MN35 is connected to the diode-connected NMOS transistor MN34. At this time, a current mirror is formed at the PMOS transistor MP33 and the diode-connected PMOS transistor MP31, which is an active load, so that a bias current is mirrored at the NMOS transistor MN35 through the NMOS transistor MN34.
Accordingly, the current of NMOS transistor MN35 for current sinking increases in proportion to the size ratio of the NMOS transistors MN35 and MN33 so that the PMOS transistor MP34 and the NMOS transistor MN35 are operated as push-pull drivers.
The above-mentioned push-pull operational amplifier has better power consumption and current drivability characteristics than the operational amplifiers shown in FIGS. 1 and 2. However, because the maximum current sinking drivability is a value multiplying a current I flowing in the NMOS transistor MN33 and a size ratio of NMOS transistors MN34 and MN35, the current sinking drivability of the NMOS transistor MN35 is lower compared with the current source drivability of the PMOS transistor MP34. So, in order to improving the current sinking drivability of the NMOS transistor MN35, the current I or the size ratio of the NMOS transistors MN35 and MN34 has to increase, which undesirably increases static power consumption.
In accordance with one aspect of the disclosure, an operational transconductance amplifier may include a differential amplification unit adapted to generate a first output signal and a second output signal through first and a second output nodes by differentially amplifying first and second differential input signals, a driving unit adapted to charge or discharge an output load in response to the first and second output signals, and a driving current control unit adapted to control the driving current of the driving unit in response to the first output signal.
In accordance with another aspect of the disclosure, an operational transconductance amplifier may include a differential amplification unit for differentially amplifying first and second differential input signals and for outputting first and second output signals through first and second output nodes, a driving unit adapted to charge or discharge an output load of an output node in response to the first and the second output signals of the differential amplification unit, and a driving current control unit adapted to control a sinking current of the driving unit for discharging the output load of the output node in response to the first output signal of the differential amplification unit.
In accordance still another aspect of the disclosure, an operational transconductance amplifier may include a differential amplification unit adapted to differentially amplify first and second differential input signals and to output first and second output signals through first and second output nodes, a driving unit adapted to charge or discharge an output load of an output node in response to the first and the second output signals of the differential amplification unit, and a driving current control unit adapted to control a sourcing current of the driving unit for charging the output load of the output node in response to the first output signal of the differential amplification unit.